Not Applicable.
Not Applicable.
The present embodiments relate to digital data circuits, and are more particularly directed to systems requiring the passage of information between different clock domains.
Digital systems often include circuits operating at different clock rates, and often there is a need to communicate information between such circuits while accommodating the accompanying change in clock rate between the circuits. Such information may include one or more bits in the form of control signals, flags, or other state indicators. In any event, the bit(s) cannot be directly communicated between circuits operating at different clock speeds due to potential metastability problems. By way of further explanation, such metastability problems may occur because if a circuit operating a first clock speed attempts to sample a bit state from a circuit operating at a second clock speed, there is the possibility that the sampled bit state may change at the instant it is being sampled. If this occurs, the resulting sample may be unstable, possibly fluctuating between low and high before settling on one of the values in a non-deterministic manner. Indeed, the resulting sample also may take on a value that is neither a digital high (e.g., 1) nor a digital low (e.g., 0) which is clearly an undesirable and problematic result. Lastly, note that the preceding discussion regarding passing information across different clock speeds also applies in general to circuits operating at the same clock speeds, but where the circuits are asynchronous with respect to one another. In other words, in this instance, a data bit cannot be directly passed from one circuit to another asynchronously operating circuit without the risk of an erroneous or invalid sampling of that bit. Given the two different scenarios now provided (i.e., different clock speeds or same but asynchronous clock speeds), and for purposes of definition for the remainder of this document, both may be collectively referred to as examples of crossing clock domains. In other words, both examples demonstrate a first circuit operating in a first clock domain and passing information to a second circuit operating in a second and different clock domain.
By way of further background, FIG. 1 illustrates a block diagram of a prior art system 10 which addresses the cross-domain issues raised above, and more particularly system 10 illustrates an example where different clock speeds are used by different circuits and information is communicated between those circuits. System 10 includes two state machines and, for sake of reference, a first is shown as state machine A while a second is shown as state machine B. Each of state machines A and B is clocked according to a respective clock signal CLKA and CLKB, where these clock signals are at different speeds. As an example, assume that CLKA equals 25 MHz while CLKB equals 100 MHz. Accordingly, and as detailed below, system 10 represents an example of two circuits, which are illustrated by way of example as state machines, where it is desired for request information to be communicated between those circuits. For reasons detailed later, the passage of such information in the prior art requires a first communication path from state machine A to state machine B, and a second communication path from state machine B to state machine A. Each of these paths is described separately, below.
Looking to the path of communication from state machine A to state machine B, state machine A has a SET control signal and a CLEAR control signal coupled to a flag F1. Flag F1 may represent various types of information, where for the present example assume that flag F1 is a one-bit indicator from state machine A that, in response to a setting of the flag, state machine B is to take some action. The action of state machine B may be completely unrelated to state machine A or, alternatively, it may related to state machine A (e.g., such as state machine B taking action with respect to data, where the data also relates in some manner to state machine A). The state of flag F1 is connected to an input of a synchronizer SAB, and the output of synchronizer SAB is connected to state machine B. Synchronizer SAB is constructed such that its input is connected to the data input of a latch LAB1, and the output of latch LAB1 is connected to the data input of a latch LAB2. The output of latch LAB2 provides the output of synchronizer SAB and, thus, as stated above, is connected to state machine B. Lastly, both of latches LAB1 and LAB2 are docked by CLKB.
Looking to the path of communication from state machine B to state machine A, note that state machine B is also operable to provide a one-bit CONFIRM control signal to state machine A via a synchronizer SBA where the functionality of the CONFIRM signal is described later. More particularly with respect to the CONFIRM signal, it is connected to the input of a synchronizer SBA, and the output of synchronizer SBA is connected to state machine A. Synchronizer SBA is constructed such that its input is connected to the data input of a latch LBA1, and the output of latch LBA1 is connected to the data input of a latch LBA2. The output of latch LBA2 provides the output of synchronizer SBA and, thus, as stated above, is connected to state machine A. Lastly, both of latches LBA1 and LBA2 are clocked by CLKA.
The operation of system 10 is now described, with particular emphasis on the notion of communicating information across clock domains from state machine A to state machine B. By way of example, assume that the cross-domain information is the state of flag F1. Further, when the state of flag F1 is changed by state machine A, the change ultimately is detected by state machine B so that in response to that change state machine B may take a corresponding action. Thus, assume at a given time that state machine A is ready to request an action of state machine B. At this time, state machine A indicates this status by asserting its SET control signal and thereby setting flag F1. At the first assertion of CLKB following the setting of flag F1, latch LAB1 latches the set flag. At the second assertion of CLKB following this assertion of SET, latch LAB2 latches the set flag F1 from latch LAB1, and thereby provides it to state machine B. Note, therefore, that communication of the set flag consumes two CLKB periods. Next, and in response to the set flag F1, state machine B takes the necessary action in response to the set flag F1.
After state machine B has taken its action, state machine B is required to acknowledge to state machine A that state machine B has responded to the set flag F1. Accordingly, state machine B provides such an acknowledgment via its CONFIRM signal and through synchronizer SBA. More particularly, state machine B asserts the CONFIRM signal and, at the first assertion of CLKA following the assertion of the CONFIRM signal, latch LBA1 latches the asserted CONFIRM signal. At the second assertion of CLKA following the assertion of the CONFIRM signal, latch LBA2 latches the asserted CONFIRM signal, and thereby provides it to state machine A. Further with respect to this communication, however, note the required use of clock cycles in this regard. Specifically, recall that synchronizer SBA is clocked by CLKA and, hence, at 25 MHz. Thus, when state machine B asserts the CONFIRM signal, it cannot assert it only for one period of CLKB because, in that case, there is a chance that CLKA will not transition during that one period of CLKB and, if this failure occurs, then the asserted CONFIRM signal will not be latched by latch LBA1. Indeed, given the example speeds of CLKA equal to 25 MHz and CLKB equal to 100 MHz, one skilled in the art should appreciate that to ensure proper latching of the CONFIRM signal state machine B must maintain its assertion of that signal for at least five cycles of CLKB, because in doing so there is then a sufficient time period during which the CONFIRM signal is asserted so that CLKA will assert at least once during that time period. Finally, note that communication of the CONFIRM signal to state machine A also consumes two CLKA periods so that the signal may pass through the latches of synchronizer SBA.
In addition to the acknowledgment from state machine B to state machine A, state machine B also controls the CONFIRM signal to ensure that it is de-asserted after it is asserted because only after the CONFIRM signal is de-asserted will state machine A assert its CLEAR control signal to flag F1 and thereby clear that flag. This additional requirement is imposed in the prior art because without it there would be the risk that state machine A could assert flag F1 two times for two different actions to be taken by state machine B, but with the result that the two asserted flags would overlap and thereby be perceived by state machine B as a single request to take action. In any event, attention is now directed to the required use of clock cycles with respect to the de-assertion of the CONFIRM signal by state machine B. Specifically, because the de-assertion also is latched through synchronizer SBA, then for the same reasons set forth above with respect to state machine B asserting the CONFIRM signal, the de-assertion of that signal by state machine B also must be maintained for at least five periods of CLKB (again, to ensure that CLKA is asserted at least one during the de-assertion of CONFIRM to thereby latch the de-assertion into latch LBA1). Finally, note that clearing of the CONFIRM signal to state machine A also consumes two CLKA periods so that the cleared signal may pass through the latches of synchronizer SBA.
Given the preceding, the present inventor has recognized that the entire number of clock cycles given the configuration and requirements of system 10 may be considerable from the time between an instance where state machine A requests an action to be taken by state machine B, and the next instance where state machine A is able to again request an action to be taken by state machine B. Indeed, these delays can be problematic when trying to pass information at high repetition rates. Finally, it is noted for the example numbers set forth above that the absolute minimum delay is 10 periods of CLKB per action item to be taken by state machine B, and this further assumes that state machines A and B take zero time.
In view of the above, there arises a need to address the drawbacks of the prior art and to provide a system that efficiently permits the passage of information between different clock domains, and this need is satisfied by the preferred embodiment described below.
In the preferred embodiment, there is a system for communicating request information from a first circuit operable according to a first clock domain to a second circuit operable according to a second clock domain. In the system, the first clock domain differs from the second clock domain. The system comprises a flag circuit for storing a flag having a changeable state. The flag circuit comprises an input for receiving a toggle control signal and the state of the flag changes in response to assertion of the toggle control signal, where the first circuit is operable to assert the toggle signal to communicate the request information to the second circuit. The system further comprises a synchronizing circuit having an input coupled to an output of the flag circuit and for receiving the state of the flag. The system further comprises a detection circuit having an input coupled to an output of the synchronizing circuit. The detection circuit is operable to detect a change in the state of the flag and to output a detection control signal to the second circuit in response to detection a change in the state of the flag. Other circuits, systems, and methods are also disclosed and claimed.